What about latency when using dual routing mode? Is it similar to normal routing, as in with both algorithms on a single path in series, that path will have a latency of 4,5 ms and in parallel 3,8 ms?
What about when you move one algorithm to path 1 and the other to path 2? What will be the latency for the individual paths?
I have the H90 in/out 1 in a true bypass loop switcher, so that I can remove the first path entirely from the signal path when I don’t use it. Can I reduce the overall latency of a path by moving one algorithm to the unused path?
How much of the latency is caused by A/D/A conversions and how much is actual processing latency? I assume from the series vs parallel numbers that the algos run on separate cores and passing the signal between cores adds around 0,7 ms?
