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I’ve implemented the capacitor modelling approach to DADSR as an alternative.  It should be less processor intensive and a little more elegant than the previous attempt.  I’ve also provided a white paper as to how I implemented this, that tells you which blocks to wire into if you wish to use this in your own VSIG creations (please read the white paper prior to using the VSIG code).

This provides a 5 stage (Delay, Attack, Decay, Sustain, Release) unipolar envelope with the output being updated at the sampling rate.  The envelope modelling takes account of your chosen sampling rate.  The capacitor model allows for easily expanding the envelope to implement additional stages, by creating step changes for each step, with the exponential curves being automatically calculated.

The white paper and the VSIG file is available at https://godlike.com.au/index.php?id=420

Any feedback would be appreciated.  This is my first low level modelling done on VSIG.