Download the Exponential DADSR Proof of concept. There’s a bit of a manual. I haven’t implemented the fix for a potential glitch if you release before reaching the sustain section, but will have a go when I get a chance. If you build a better one, please upload and share.
I’ve implemented the capacitor modelling approach to DADSR as an alternative. It should be less processor intensive and a little more elegant than the previous attempt. I’ve also provided a white paper as to how I implemented this, that tells you which blocks to wire into if you wish to use this in your own VSIG creations (please read the white paper prior to using the VSIG code).
This provides a 5 stage (Delay, Attack, Decay, Sustain, Release) unipolar envelope with the output being updated at the sampling rate. The envelope modelling takes account of your chosen sampling rate. The capacitor model allows for easily expanding the envelope to implement additional stages, by creating step changes for each step, with the exponential curves being automatically calculated.
I’ve updated this (same link as before). I added a much more efficient implementation of capacitor modelling by utilizing the integrator block. This also provides a demonstration of how to use the integrator block effectively (because it is a tricky little thing).