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April 16, 2008 at 12:02 am #105584
I want to create a set of basic supermodules to ease design of algorithms.
My problem is that if I have a super module algorithm that takes say In1 and sends it to 3 different inputs of modules, then the compiled supermodule displays all the inputs to all embedded modules. I tried inserting a A_TO_A "dummy" between In1 and where In1 has to go, hoping that the supermodule would show this, but then as I try to save the file, Vsigfile tells me that I should save it as a sif file, not a sig file.
So my question simply is how do you create a supermodule that only has two visible inputs and two visible outputs for stereo?
April 16, 2008 at 6:33 am #117387IDeangelisMember
from Vsig manual:
A supermodule is created by
selecting the required modules, and then using the Create
Supermodule command. All connections, connectors and fields of the component modules
will then be hidden, except for those connected to points outside the
supermodule. For this reason it is worth making the external connections to the
modules that will comprise the supermodule first.
You may want to connect all the needed inputs and outputs before creating a supermodule. When you save it, all I/Os will be properly displayed then.
When you "Add to Library" a supermodule, it is saved as.sif. The Library is the place where you want to add Supermodules to have them available for later work as a group of modules in the same list where all other modules belong.
April 16, 2008 at 2:35 pm #117389
It's working great now. I just combined two supermodules and it works fine in the H7600.
I'm building a library of SM's now, as it makes combining pieces so much simpler.
April 17, 2008 at 2:29 am #128512DaveFXParticipant
I'm glad you're doing stuff with VSIG!
Here's another tip. When I want a supermodule audio input to act like an audio node or binding post, I use a BOUND module inside the supermodule instead of A_TO_A. Then VSIG saves that without complaining. I set the limits of the BOUND to be wide open so it doesn't affect the audio.
April 17, 2008 at 1:32 pm #128513
Thanks. I'll try it now. Is it CPU expensive?
April 17, 2008 at 3:55 pm #128517IDeangelisMember
Not much…but if you combine several supermodules in a sigfile..and it's getting a big one….these modules may take some dsp cycles needed by other resources. Sometimes an algorithm may be "on the edge" and little adjustments may help it loading & running.
Everything depends on size and resources here, so you may remember to remove unecessary modules if needed.
April 18, 2008 at 2:22 am #128520DaveFXParticipant
I agree with that. I also just checked my assumptions using VSIG 188.8.131.52 with my H8000FW modules database 5.2:
- If I save and open a file as .sif (the binary format), then VSIG saves the nodes A_TO_A and C_TO_C (in a supermodule, too).
- If I save and open a file as .sig (the ASCII format), then VSIG removes the nodes A_TO_A and C_TO_C.
Ideally, I might like VSIG to save nodes in .sig (where I could use them for some supermodule inputs), but I?ll put my fantasy in perspective:
- Of all H8000FW/H7600 users, some use VSIG.
- Of all VSIG users, some use supermodules.
- Of all supermodule users, some use input nodes.
- Of all node users, some insist on saving as .sig.
Maybe that?s only me… one user worldwide!
April 18, 2008 at 11:45 am #128523
Make that 2 of us then. I have been using BOUND and it's great.
I am a now steering away from the MIDI Racks, because I find that I can't add too much to them on my H7600. But in the process, I ma developing some interesting stuff, and supermodules are definitely a requirement for me.
I mean, can you imagine writing c++ code without classes?
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