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March 3, 2018 at 2:47 am #148562
I’m curious about memory management on the H9000 from the user’s point of view. On the Orville / H8000 it was sort of simple: each engine had a 47 second pool of delay memory to split amongs all modules, and engine A also had 174 seconds of Sample Memory.
How will all this work on the H9000? My assumptions are that each ARM chip has its own memory pool, and that the four cores share that memory pool. How is memory allocated between the four cores on an ARM chip? What are the user’s responsibllity in managing this memory?