Sounds good! Do you have any more info about the goodies? Any idea if running of 2 algorithms per core is currently being worked on? And routing between different DSPs perhaps?
You can already run 4 algorithms on each CPU, and you can use VSIG to multi-purpose any of those algorithms up to the CPU processing limit.
No ability to send between chains yet though, but an internal send and receive block between CPU’S would be amazing.
I’d love to see super blocks make a return.